Semiconductor device having carbon nanotube interconnects and method of fabrication

ABSTRACT

An integrated circuit having carbon nanotube interconnects contains input/output pads situated on the upper surface, the pads arranged in an array having at least two rows. Carbon nanotubes are disposed on the input/output pads to provide electrical and thermal interconnection of the integrated circuit chip to another circuit such as a printed circuit board. The carbon nanotubes can be plated with one or more overlayers of metal.

FIELD OF THE INVENTION

This invention relates generally to semiconductor devices. Moreparticularly, this invention relates to semiconductor devices that havecarbon nanotubes incorporated into the semiconductor device interconnectstructure, and a method for forming the carbon nanotube interconnectstructure.

BACKGROUND

Electronic device miniaturization requires ever smaller semiconductordevice packaging technologies. One such technology is a wafer levelpackage. The wafer level package is a type of chip scale package whichenables the integrated circuit (IC) die to be attached directly to aprinted circuit board (PCB) face down, that is, with the IC'sinput/output (I/O) pads connecting to the PCB's pads through individualsolder balls. This technology differs from other types of packagesbecause there are no bond wires or interposer substrates. The principleadvantage of the wafer level package is that the IC-to-PCB inductance isminimized. Secondary benefits are reduction in package size andmanufacturing cycle time and enhanced thermal conductioncharacteristics, because today's faster semiconductor devices areoperating at higher frequencies and thus generate significantly moreheat. This traditional wafer level package and interconnect technologyusing solder bumped pads works well electrically and thermally down to0.25 mm I/O pitch, but further miniaturization of pitch to accommodatevery high I/O devices running at very high speeds may not be possiblewith this technology. The problem with the current art is the inabilityto have very fine pitch full array interconnects that have adequateaspect ratio (height-to-width) and conductivity for optimal performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, where like reference numerals refer toidentical or functionally similar elements throughout the separate viewsand which together with the detailed description below are incorporatedin and form part of the specification, serve to further illustratevarious embodiments and to explain various principles and advantages allin accordance with the present invention.

FIG. 1 is a perspective view of an integrated circuit having carbonnanotube interconnects in accordance with certain embodiments of thepresent invention.

FIG. 2 is a cross-sectional view of a portion of FIG. 1 in accordancewith certain embodiments of the present invention. The relative size ofsome elements has been exaggerated for clarity.

FIG. 3 is a process flow chart depicting some of the steps of forming anintegrated circuit having carbon nanotube interconnects in accordancewith certain embodiments of the present invention.

DETAILED DESCRIPTION

As required, detailed embodiments of the present invention are disclosedherein; however, it is to be understood that the disclosed embodimentsare merely exemplary of the invention, which can be embodied in variousforms. Therefore, specific structural and functional details disclosedherein are not to be interpreted as limiting, but merely as a basis forthe claims and as a representative basis for teaching one skilled in theart to variously employ the present invention in virtually anyappropriately detailed structure. Further, the terms and phrases usedherein are not intended to be limiting; but rather, to provide anunderstandable description of the invention. The terms a or an, as usedherein, are defined as one or more than one. The term plurality, as usedherein, is defined as two or more than two. The term another, as usedherein, is defined as at least a second or more. The terms includingand/or having, as used herein, are defined as comprising (i.e., openlanguage).

An integrated circuit having carbon nanotube interconnects contains aplurality of input/output pads disposed on an upper layer thereof, thepads arranged in an array having at least two rows. Carbon nanotubes aredisposed on the input/output pads so as to provide electrical andthermal interconnection of the integrated circuit chip to anothercircuit such as a printed circuit board. The carbon nanotubes canoptionally be plated with one or more overlayers of metal. Referring nowto FIG. 1, a semiconductor device, such as an integrated circuit 100typically consists of a silicon chip 110, cut from a silicon wafer, thathas circuitry, such as transistors, interconnects, input and output padsor terminals 130, etc. on an upper surface 120. Traditionally, some ofthe circuitry is covered by a passivation layer to protect the sensitivetransistors from environmental damage. The input/output (I/O) pads 130are redistributed on a topmost layer in a full or partial array that isat least two rows wide, such that some, or all, of the pads are notcovered by the passivation layer, but are exposed. Referring now to FIG.2, a carbon nanotube or a clump of carbon nanotubes 210 is disposed onthe individual input/output pads 130. Carbon nanotubes are molecularstructures that can be either electrically conductive or semiconductive.In addition they have excellent thermal properties along an axisparallel to the tube wall. The measured thermal conductivity for asingle tube is greater than 3000 W/meter-°K. In addition to the uniqueelectrical and thermal properties of carbon nanotubes, they are capableof being fabricated with very high aspect ratios with geometries of 150micron height and 30 micron diameter. The carbon nanotubes adhere to theI/O pads sufficient to provide mechanical connection, electricalconnection, and thermal connection between the integrated circuit 100and another circuit, such as a printed circuit board (not shown).Optionally, the carbon nanotubes 210 are plated with one or more metallayers 220, 230, 240 to provide additional environmental protection andto enhance solderability of the I/O pads. The metal layers 220, 230, 240can be copper, nickel, gold, platinum, tin, lead, or alloys thereof.

Having now described the arrangement of the various structural elementsof our invention, we now describe, with reference to FIG. 3, a processfor fabricating an integrated circuit having carbon nanotubeinterconnects. An integrated circuit has I/O pads redistributed on a toplayer in a full or partial array that is at least two rows deep (310).The exposed portions of the I/O pads on the integrated circuit arecovered with carbon nanotubes (320) and/or carbon nanotubes withmetallic overlayers. The nanotubes provide a means for electrical andthermal interconnect of the integrated circuit to a next level substratewhich can be an interposer substrate or motherboard. The carbonnanotubes are formed in traditional fashion such as vapor phasedeposition from ferrocene and xylene. After the nanotubes are grown onthe substrate they are overplated with electroless copper, with thecarbon nanotube providing the catalyst and nucleation agent for theelectroless copper (340). Because no additional catalyst is needed toinitiate the electroless plating process on the carbon nanotube, thenanotube is the only surface that will plate, thus preventing shortingbetween the I/O pads. The plating process can be applied to nanotubesthat are conductive or semiconductive, individual or clumped. After theelectroless copper plating is completed, secondary layers of electrolessnickel and gold may also be plated on the copper (350, 360).

In an alternate embodiment, the carbon nanotubes are deposited over theentire surface of the integrated circuit, and then patterned to removethe excess nanotubes from all locations except the I/O pads (330).

In summary, without intending to limit the scope of the invention,fabrication of an integrated circuit having carbon nanotubeinterconnects according to a method consistent with certain embodimentsof the invention can be carried out by depositing carbon nanotubes onthe I/O pads of an integrated circuit and plating the nanotubes withmetal. This enables very dense flip chip and wafer scale packaging ofhigh I/O count integrated circuits that require interconnects with goodsecond level electrical and thermal conductivity. The copper and/orcopper-nickel-gold plated overlayers significantly increase theelectrical conductivity of the carbon nanotubes without degrading theirthermal conductivity. In addition the metallic overlayers enabletraditional next level attachment techniques such as solder orconductive adhesives.

Those skilled in the art will recognize that the present invention hasbeen described in terms of exemplary embodiments based upon use of asilicon integrated circuit chip. However, the invention should not be solimited, since other variations will occur to those skilled in the artupon consideration of the teachings herein, and many alternatives,modifications, permutations and variations may become apparent in lightof the foregoing description. Accordingly, it is intended that thepresent invention embrace all such alternatives, modifications andvariations as fall within the scope of the appended claims.

1. An integrated circuit having carbon nanotube interconnects,comprising: an integrated circuit chip having a plurality ofinput/output pads disposed on an upper layer thereof, said pads arrangedin an array having at least two rows; and carbon nanotubes disposed onthe plurality of input/output pads sufficient to provide electrical andthermal interconnection of the integrated circuit chip to anothercircuit.
 2. The integrated circuit having carbon nanotube interconnectsas described in claim 1, wherein the carbon nanotubes are plated withelectroless copper.
 3. The integrated circuit having carbon nanotubeinterconnects as described in claim 2, wherein the copper platednanotubes are further plated with an additional layer of nickel.
 4. Theintegrated circuit having carbon nanotube interconnects as described inclaim 3, wherein the copper plated nanotubes are further plated with anadditional layer of gold.
 5. An integrated circuit having carbonnanotube interconnects, comprising: an integrated circuit chip having aplurality of input/output pads disposed on an upper layer thereof, saidpads arranged in an array having at least two rows; carbon nanotubesdisposed on the plurality of input/output pads; and one or more metallayers plated on the carbon nanotubes sufficient to provide electricaland thermal interconnection of the integrated circuit chip to anothercircuit.
 6. The integrated circuit having carbon nanotube interconnectsas described in claim 5, wherein the one or more metal layers isselected from the group consisting of copper, nickel, gold, platinum,tin lead, and alloys thereof.
 7. A method of forming an integratedcircuit having carbon nanotube interconnects, comprising: providing anintegrated circuit chip having a plurality of input/output pads disposedon an exposed layer thereof; disposing carbon nanotubes over at least aportion of the exposed layer, so as to cover at least a portion of theplurality of input/output pads; and providing an overlayer of copper onat least a portion of the carbon nanotubes from a solution ofelectroless copper such that the carbon nanotube acts as a catalyst andnucleation agent for the copper.
 8. The method as described in claim 7,further comprising, after disposing the carbon nanotubes, patterningsaid disposed carbon nanotubes sufficient to remove carbon nanotubesfrom all portions of the exposed layer except the plurality ofinput/output pads.
 9. The method as described in claim 7, furthercomprising, after providing an overlayer of copper, providing a layer ofnickel on the copper.
 10. The method as described in claim 9, furthercomprising, after providing an overlayer of nickel, providing a layer ofgold on the nickel.